The present invention is in the field of serial data transmission as it applies to computerized semiconductor devices, and pertains more particularly to methods and apparatus for achieving low feed-through and consistent transition delay in a multiplexor circuit.
The present application is related to a disclosure document #487065 filed in the USPTO on Jan. 4, 2001 entitled xe2x80x9cMethod for Achieving Low Feed Through and Consistent Transition Delay in a Multiplexor Circuitxe2x80x9d
The art of designing and implementing Large Scale Devices (LSI) and very large scale integration (VLSI) devices in digital logic has become more complex and sophisticated in recent years. Sophisticated software design tools and automated techniques have replaced prior pencil and paper engineering practices once used to design semiconductor devices. As semiconductor devices have become more complex in terms of circuitry and design with shrinking device geometry, requirements for data transmission between such devices and on individual ones of such devices have also become more complex and demanding to maintain in operation.
The preferred system used for data transmission between IC devices has long been the system of parallel data transfer. The current parallel method of passing data between such devices incorporates the use of a plurality of separate data-signal transmission paths in parallel. Data passed between two communicating devices travels across a circuit board on a plurality of parallel traces or lines. For a 16-bit system, for example, there will be in a parallel system a separate trace for each bit (16 traces) plus control lines.
Generally speaking, much operational and specification data regarding the manufacture and operation of VLSI and LSI type devices is known and available in the art. Manufacturers of such devices provide exhaustive documentation, and virtually all such documentation is available to the skilled artisan. Therefore detailed architectural and functional descriptions of known IC devices are not provided herein. It is enough to say that parallel data must be clocked, synchronized and latched in order to enable successful transmission of the data from a propagating device to a receiving device over a circuit board containing a substantially large number of traces.
Another system for transferring data in general, and also sometimes used for transferring data between IC devices, is the well-known serial system. The current art serial method of transferring high bandwidth data between IC devices involves the use of encoding and decoding circuits on each communicating device to manipulate or convert parallel data so that it may be transmitted serially across a circuit board from one device to another. For example, a parallel to serial data converter in a sending device enables data to be prepared for transmission out in a serial manner using a single data line for one-way transmission. A decoder circuit in a receiving device decodes the serial data using a pre-determined decoding scheme then processes the data. At a given clock speed for both types of transmission, serial data transfer is typically slower than parallel transfer. Therefore, a high-speed clock is typically used with the serial method to speed up transmission of serial data between devices.
Another problem with serial data transfer between IC devices in current technology is that analog circuitry is typically required in the IC devices to effect the system. Analog circuitry is known to be notoriously more difficult to implement than digital circuitry, and makers of digital IC devices are not anxious to suffer the yield losses attendant on adding analog circuitry to their devices.
Still, even with the known and perceived disadvantages of serial data transmission, the high cost and complexity of parallel systems is an increasing problem. As computing systems have matured from 4 to 8 to 16 to 32 bit words, and as microprocessors and memories (for example) have become more functional and sophisticated, the number of traces and pins necessary to accomplish adequate transmission has increased dramatically. It is, for example, common now to have plural sets of parallel data transmission pathways serving a single IC device. The high number of traces necessary on a PC board (for example) makes such support systems enormously complex and expensive to design and manufacture. Moreover, every trace demands a separate pin on the IC device. Many devices have more than two hundred pins, and future devices may demand even more. The ever increasing pin counts inherent to such devices makes such devices more complex to build and increases losses (low yield) in fabrication.
A serial communication system used between two or more IC devices is known to the inventor. The system utilizes a separate master chip connected to both of the IC devices, the master chip having a clock generator and circuitry for affecting serial data transmission and control between the master chip and the devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment, all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.
It is known in the art of digital logic that a multiplexor circuit is used to multiplex more than one digital input on to a single output line. Technically, this process is known as Time Division Multiplexing (TDM). High-speed multiplexing is typically implemented with Current Mode Logic CML gates. A relatively high current is required to operate a CML multiplexor at desired clock frequencies. As a result, standard CML multiplexors exhibit some performance problems related to standard prior-art design and the higher current applied as compared to other multiplexor circuits such as a CMOS multiplexor. In a standard CML multiplexor there are two input pairs that are alternately selected via two select lines for multiplexing to the output of the circuit. When one of the input pairs is disabled (not selected) it is still directly connected to the output of the multiplexor. This creates a capacitive path from the input pair to the output pair. The resulting undesirable phenomenon is known as feed-through in the art. Another problem is that the internal nodes of the disabled input structure, in particular the source terminals of the input pair, are allowed to float. This causes the source voltage to be poorly defined when the pair is again selected. This uncertainty of proper voltage translates into an uncertainty in the time from the instant of selecting this previously disabled pair to a time when the output stabilizes. It is, of course, desired that these phenomena be largely reduced in order to improve performance of a multiplexor circuit.
Therefore, what is clearly needed is a multiplexor circuit design that will provide symmetry to a multiplexing operation so that feed-through is sharply reduced, certainty of voltage and timing is improved and therefore predictability in operation is greatly enhanced.
In a preferred embodiment of the present invention, a multiplexor circuit for performing time-division-multiplexor is provided. The mulitplexor circuit comprises, two or more input signal pairs, the pairs comprising individual signal lines for providing timed data input into the multiplexor circuit, the pairs alternately selectable for operation, two or more select lines for selecting alternate ones of the input signal pairs during operation, one or more output lines comprising signal output of the circuit and two or more resistive output loads and associated electronic gates. When a specific one or ones of the input pairs is not selected for output, the non-selected input pair is not directly connected to the output lines of the circuit, eliminating the capacitive feed through, but is instead connected to an individual one or ones of the resistive output loads enabled by the associated gates to initialize the internal voltages of the non-selected structure to the voltages they would be if the input was selected, to greatly reduce the variation in settling time when this output is later selected.
In a preferred embodiment, the circuit is implemented with current mode logic. In one embodiment, the circuit is implemented on a single IC device. In another embodiment, the circuit is implemented on more than one separate but connected devices.
In another aspect of the present invention, a method for reducing capacitive feed-through and timing uncertainty from a non-selected signal-input pair to output of a multiplexor circuit, the circuit having at least one additional resistive output load and associated electronic gates is provided. The method comprises the steps of, (a) changing the selection structure from a current steering selection to a switching selection connected to the output nodes, (b) dividing the current sinking capabilities to accommodate the separate input structures that are no longer supplied current by the selection structure and (c) providing at least one additional resistive output load and associated electronic gates to maintain the biasing of these current sinks and initialize the internal voltages of the non-selected structure to the voltages they would be if the input was selected.
In a preferred embodiment, the circuit is implemented with current mode logic. In one aspect of the method steps (a)-(c) are accomplished with circuitry implemented on a single IC device. In another aspect of the method in steps (b) and (c), the number of additional current sinking structures and output loads and associated electronic gates is directly proportional to the number of input pairs that are not selected to output at any given time during operation of the circuit.
Now, for the first time, a multiplexor circuit design that will provide symmetry to a multiplexing operation so that feed-through is sharply reduced and timing certainty and therefore predictability in operation is greatly enhanced is provided.